$DD00/56576/CIA2+0:   Data Port A (Serial Bus, RS232, VIC Base Mem.)

   +----------+---------------------------------------------------+
   | Bit  7   |  Serial Bus Data Input                            |
   | Bit  6   |  Serial Bus Clock Pulse Input                     |
   | Bit  5   |  Serial Bus Data Output                           |
   | Bit  4   |  Serial Bus Clock Pulse Output                    |
   | Bit  3   |  Serial Bus ATN Signal Output                     |
   | Bit  2   |  RS232 Data Output (User Port)                    |
   | Bit  1-0 |  VIC Chip System Memory Bank Select (low active!) |
   +----------+---------------------------------------------------+

   Default Value: $17/23 (%00010111)

By Oswald/Resource.

VICII can only adress 16k ram at once. This means that the 64k memory is divided into four 16k VIC banks. $DD00's lowmost 2 bits controls that which bank is seen by the VIC:

$DD00 = %xxxxxx11 -> bank0: $0000-$3fff
$DD00 = %xxxxxx10 -> bank1: $4000-$7fff
$DD00 = %xxxxxx01 -> bank2: $8000-$bfff
$DD00 = %xxxxxx00 -> bank3: $c000-$ffff

$DD00 should be handled with care when also loading while changing VIC bank, because the other bits in it are controlling the serial transfer. If speed is not critical its generally a good idea to change vic bank like this:

lda $DD00
and #%11111100
ora #%000000xx ;<- your desired VIC bank value, see above
sta $DD00

the above will only change the bits controlling the VIC bank position.

A little tip from Nitro/Black Sun: If you are using Krill's loader to change the banks, just do

lda #%000000xx ;<- your desired VIC bank value, see above
sta $dd00

Otherwise it won't work.

Kernal-Reference:

 CMP $DD00   : $ED69 $EE5D $EE6A $EEAC
 LDA $DD00   : $ED2E $ED66 $ED84 $EDBE $EDF3 $EE5A $EE67 $EE85 $EE8E $EE97
               $EEA0 $EEA9 $FE7B
 ORA $DD00   : $F492
 STA $DD00   : $ED33 $ED8B $EDC3 $EDF8 $EE8A $EE93 $EE9C $EEA5 $F495 $FDCD
               $FE82